Evaluating stream buffers as a secondary cache replacement
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Informed prefetching and caching
SOSP '95 Proceedings of the fifteenth ACM symposium on Operating systems principles
A memory selection algorithm for high-performance pipelines
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Parallel Computing - Special double issue: parallel I/O
Analysis of power consumption in memory hierarchies
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Dependence based prefetching for linked data structures
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Adapting cache line size to application behavior
ICS '99 Proceedings of the 13th international conference on Supercomputing
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
Access pattern based local memory customization for low power embedded systems
Proceedings of the conference on Design, automation and test in Europe
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
A Language for Conveying the Aliasing Properties of Dynamic, Pointer-Based Data Structures
Proceedings of the 8th International Symposium on Parallel Processing
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Flow Graph Balancing for Minimizing the Required Memory Bandwidth
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Shade: A Fast Instruction Set Simulator for Execution Profiling
Shade: A Fast Instruction Set Simulator for Execution Profiling
Access pattern-based memory and connectivity architecture exploration
ACM Transactions on Embedded Computing Systems (TECS)
Memory Architectures for Embedded Systems-On-Chip
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
Proceedings of the 40th annual Design Automation Conference
Processor-memory coexploration using an architecture description language
ACM Transactions on Embedded Computing Systems (TECS)
Memory access driven storage assignment for variables in embedded system design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Layer Assignment echniques for Low Energy in Multi-Layered Memory Organisations
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Memory access pattern analysis and stream cache design for multimedia applications
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Processor Description Languages
Processor Description Languages
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Memory accesses represent a major bottleneck in embedded systems power and performance. Traditionally, designers tried to alleviate this problem by relying on a simple cache hierarchy, or a limited use of special purpose memory modules such as stream buffers. Although real-life applications contain a large number of memory references to a diverse set of data structures, a significant percentage of all memory accesses in the application are generated from a few memory instructions that exhibit predictable, well-known access patterns; this creates an opportunity for memory customization, targeting the needs of these access patterns. We present APEX, an approach that extracts, analyzes and clusters the most active access patterns in the application, and aggressively customizes the memory architecture to match the needs of the application, exploring a wide range of cost, performance and power designs. We use a heuristic to prune the design space, guiding the exploration towards the best cost/gain ratios. We present experiments on a set of large real-life benchmarks, showing significant performance improvements for varied cost and power characteristics, allowing the designer to best target the system goals.