Two-level adaptive training branch prediction
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Planar-adaptive routing: low-cost adaptive networks for multiprocessors
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
The Stanford FLASH multiprocessor
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Dynamic history-length fitting: a third level of adaptivity for branch prediction
Proceedings of the 25th annual international symposium on Computer architecture
Dynamic IPC/clock rate optimization
Proceedings of the 25th annual international symposium on Computer architecture
Exploiting spatial locality in data caches using spatial footprints
Proceedings of the 25th annual international symposium on Computer architecture
Scalability of the cedar system
Proceedings of the 1994 ACM/IEEE conference on Supercomputing
Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels
IEEE Transactions on Parallel and Distributed Systems
An adaptive sequential prefetching scheme in shared-memory multiprocessors
ICPP '97 Proceedings of the international Conference on Parallel Processing
MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors
MASCOTS '94 Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems
Distributed Shared Memory Architecture for JUMP-1: A General-Purpose MPP Prototype
ISPAN '96 Proceedings of the 1996 International Symposium on Parallel Architectures, Algorithms and Networks
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Access pattern based local memory customization for low power embedded systems
Proceedings of the conference on Design, automation and test in Europe
Morphable Cache Architectures: Potential Benefits
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
APEX: access pattern based memory architecture exploration
Proceedings of the 14th international symposium on Systems synthesis
Managing multi-configuration hardware via dynamic working set analysis
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
MIST: an algorithm for memory miss traffic management
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Access pattern-based memory and connectivity architecture exploration
ACM Transactions on Embedded Computing Systems (TECS)
Compiler-Directed Cache Assist Adaptivity
ISHPC '00 Proceedings of the Third International Symposium on High Performance Computing
Compiler-Directed Cache Line Size Adaptivity
IMS '00 Revised Papers from the Second International Workshop on Intelligent Memory Systems
Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Static analysis of parameterized loop nests for energy efficient use of data caches
Compilers and operating systems for low power
A Self-Tuning Cache Architecture for Embedded Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Dynamic techniques to reduce memory traffic in embedded systems
Proceedings of the 1st conference on Computing frontiers
SAGE: an automatic analyzing system for a new high-performance SoC architecture-processor-in-memory
Journal of Systems Architecture: the EUROMICRO Journal
Improving workload balance and code optimization on processor-in-memory systems
Journal of Systems and Software
A self-tuning cache architecture for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Dynamic Platform Management for Configurable Platform-Based System-on-Chips
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache
IEEE Transactions on Computers
SCIMA-SMP: on-chip memory processor architecture for SMP
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
A highly configurable cache for low energy embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Fast configurable-cache tuning with a unified second-level cache
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Proceedings of the 33rd annual international symposium on Computer Architecture
Exploiting soft redundancy for error-resilient on-chip memory design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Increasing cache capacity through word filtering
Proceedings of the 21st annual international conference on Supercomputing
Heterogeneous associative cache for multimedia applications
IMSA'07 IASTED European Conference on Proceedings of the IASTED European Conference: internet and multimedia systems and applications
Improving SDRAM access energy efficiency for low-power embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Variable-sized object packing and its applications to instruction cache design
Computers and Electrical Engineering
Revisiting Cache Block Superloading
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Heterogeneous associative cache for multimedia applications
EurolMSA '07 Proceedings of the Third IASTED European Conference on Internet and Multimedia Systems and Applications
Exploiting memory soft redundancy for joint improvement of error tolerance and access efficiency
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive line size cache for irregular references on cell multicore processor
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Dynamically reconfigurable cache architecture using adaptive block allocation policy
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Fast configurable-cache tuning with a unified second-level cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive granularity memory systems: a tradeoff between storage efficiency and throughput
Proceedings of the 38th annual international symposium on Computer architecture
Flux caches: what are they and are they useful?
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
A survey on cache tuning from a power/energy perspective
ACM Computing Surveys (CSUR)
Protozoa: adaptive granularity cache coherence
Proceedings of the 40th Annual International Symposium on Computer Architecture
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