Line (block) size choice for CPU cache memories
IEEE Transactions on Computers
Analysis of memory referencing behavior for design of local memories
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
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Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Parallel compression with cooperative dictionary construction
DCC '96 Proceedings of the Conference on Data Compression
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ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
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ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
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ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Comparing Program Phase Detection Techniques
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Adaptive Cache Compression for High-Performance Processors
Proceedings of the 31st annual international symposium on Computer architecture
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ICCD '05 Proceedings of the 2005 International Conference on Computer Design
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Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
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With the increasing performance gap between processor and memory, it is essential that caches are utilized efficiently. However, caches are very inefficiently utilized because not all the excess data fetched into the cache, to exploit spatial locality, is accessed. Studies have shown that a prediction accuracy of about 95% can be achieved when predicting the to-be-referenced words in a cache block. In this paper, we use this prediction mechanism to fetch only the to-be-referenced data into the L1 data cache on a cache miss. We then utilize the cache space, thus made available, to store words from multiple cache blocks in a single physical cache block space in the cache, thus increasing the useful words in the cache. We also propose methods to combine this technique with a value-based approach to further increase the cache capacity. Our experiments show that, with our techniques, we achieve about 57% of the L1 data cache miss rate reduction and about 60% of the cache capacity increase observed when using a double sized cache, with only about 25% cache space overhead.