On management of free space in compressed memory systems
SIGMETRICS '99 Proceedings of the 1999 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Cache-Memory Interfaces in Compressed Memory Systems
IEEE Transactions on Computers
Hardware Compressed Main Memory: Operating System Support and Performance Evaluation
IEEE Transactions on Computers
Adaptive Cache Compression for High-Performance Processors
Proceedings of the 31st annual international symposium on Computer architecture
A compressed memory hierarchy using an indirect index cache
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
Memory State Compressors for Giga-Scale Checkpoint/Restore
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Restrictive Compression Techniques to Increase Level 1 Cache Capacity
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Increasing cache capacity through word filtering
Proceedings of the 21st annual international conference on Supercomputing
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Stateful hardware decompression in networking environment
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Algorithms and data structures for compressed-memory machines
IBM Journal of Research and Development
On internal organization in compressed random-access memories
IBM Journal of Research and Development
IBM memory expansion technology (MXT)
IBM Journal of Research and Development
Memory expansion technology (MXT): software support and performance
IBM Journal of Research and Development
Memory expansion technology (MXT): competitive impact
IBM Journal of Research and Development
Decoupled zero-compressed memory
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
C-pack: a high-performance microprocessor cache compression algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A space-efficient on-chip compressed cache organization for high performance computing
ISPA'04 Proceedings of the Second international conference on Parallel and Distributed Processing and Applications
Delta-compressed caching for overcoming the write bandwidth limitation of hybrid main memory
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
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It is often desirable to compress or decompress relatively small blocks of data at high bandwidth and low latency (for example, for data fetches across a high speed network). Sequential compression may not satisfy the speed requirement, while simply splitting the block into smaller subblocks for parallel compression yields poor compression performance due to small dictionary sizes. We consider an intermediate approach, where multiple compressors jointly construct a dictionary. The result is parallel speedup, with compression performance similar to the sequential case.