Parallel algorithms for data compression
Journal of the ACM (JACM)
A parallel architecture for high-speed data compression
Journal of Parallel and Distributed Computing
Parallel compression with cooperative dictionary construction
DCC '96 Proceedings of the Conference on Data Compression
A Corpus for the Evaluation of Lossless Compression Algorithms
DCC '97 Proceedings of the Conference on Data Compression
Design and validation of a performance and power simulator for PowerPC systems
IBM Journal of Research and Development
POWER5 System microarchitecture
IBM Journal of Research and Development - POWER5 and packaging
Efficient memory utilization on network processors for deep packet inspection
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Discrete Applied Mathematics - 12th annual symposium on combinatorial pattern matching (CPM)
IBM memory expansion technology (MXT)
IBM Journal of Research and Development
POWER4 system microarchitecture
IBM Journal of Research and Development
Exploiting heterogeneous multicore-processor systems for high-performance network processing
IBM Journal of Research and Development
Introduction to the wire-speed processor and architecture
IBM Journal of Research and Development
Packet scheduling for deep packet inspection on multi-core architectures
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Application-driven energy-efficient architecture explorations for big data
Proceedings of the 1st Workshop on Architectures and Systems for Big Data
Platform and applications for massive-scale streaming network analytics
IBM Journal of Research and Development
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Compression and Decompression can significantly lower the network bandwidth requirements for common internet traffic. Driven by the demands of an enterprise network intrusion system, this paper defines and examines the requirements of popular dictionary-based decompression in the real-time network processing scenario. In particular, a "stateful" decompression is required that arises out of the packet oriented nature of current networks, where the decompression of the data of a packet depends on the decompressed contents of its preceeding packets composing the same data stream. We propose an effective hardware decompression acceleration engine, which fetches the history data into the accelerator's fast memory on-demand and hides the associated latency by exploring the parallelism of the dictionary-based decompression process. We specify and evaluate various design and implementation options of the fetch-on-demand mechanism, i.e. prefetch most frequently used history, on-accelerator history buffer management, and reuse of fetched history data. Through simulation-based performance study, we show the effectiveness of the proposed mechanism on hiding the overhead of stateful decompression. We further show the effects of the design options and the impact on the overall performance of the network service stack of an intrusion prevension system.