Introduction to the wire-speed processor and architecture

  • Authors:

  • H. Franke;J. Xenidis;C. Basso;B. M. Bass;S. S. Woodward;J. D. Brown;C. L. Johnson

  • Affiliations:

  • IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, NY;IBM Research Division, Austin Research Laboratory, Austin, TX;IBM Systems and Technology Group, Research Triangle Park, NC;IBM Systems and Technology Group, Research Triangle Park, NC;IBM Systems and Technology Group, Rochester, MN;IBM Systems and Technology Group, Rochester, MN;IBM Research Division, Rochester, MN

  • Venue:
  • IBM Journal of Research and Development
  • Year:
  • 2010

Quantified Score

Hi-index 0.00

Visualization

Abstract

In this paper, we introduce the wire-speed processor (WSP) project, an advanced development project led by IBM Research and the IBM Systems and Technology Group. The WSP represents a generic processor architecture in which processing cores, hardware accelerators, and I/O functions are closely coupled in a system on a chip. The first implementation of the WSP architecture targets applications operating at "wire speed" (i.e., speeds in which the data are transmitted and processed at the maximum speed allowed by the hardware). These applications include those that involve routers, firewalls, intrusion-prevention systems, and other network analytics. The WSP combines 16 multithreaded IBM PowerPC® cores with special-purpose dedicated accelerators optimized for packet processing, security, pattern matching, compression, Extensible Markup Language (XML) parsing, and I/O for networking that provides four 10-Gb/s bidirectional network links. In this paper, we describe the various system components, the underlying design philosophy involving close integration of these components, and the special system features that were developed to achieve this close integration.