IEEE Transactions on Software Engineering
FPGA Accelerated Low-Latency Market Data Feed Processing
HOTI '09 Proceedings of the 2009 17th IEEE Symposium on High Performance Interconnects
Proceedings of the 2nd Workshop on High Performance Computational Finance
Evaluation of streaming aggregation on parallel hardware architectures
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Intra-Socket and Inter-Socket Communication in Multi-core Systems
IEEE Computer Architecture Letters
Introduction to the wire-speed processor and architecture
IBM Journal of Research and Development
Efficient event processing through reconfigurable hardware for algorithmic trading
Proceedings of the VLDB Endowment
Hardware acceleration in the IBM PowerEN processor: architecture and performance
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
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Financial Market IT solutions increasingly depend on ultra low latency message processing and target microseconds latencies in order to provide traders with a competitive advantages over their peers. Some solutions are available on the market, ranging from general purpose systems with advanced network cards to specialized hardware solutions based on FPGA. The novel IBM PowerENTM "Edge of Network" processor integrates network interfaces with functional accelerators and multi-threaded cores. This paper describes the design, implementation and performance evaluation of a Market Data Feed solution based on the PowerEN processor. The paper details the SoC mechanism designed to reduce latency and increase throughput and shows how these can be used to build a Market Data Feed solutions that achieves performance figures usually obtainable only by special hardware. This prototype described achieves an average latency of 6.7 μs for an OPRA v2 feed and is able to process 1M updates per second on 2 hardware thread, achieving more than 16M updates per second on a single chip solution without consuming all the resources and thus being able to also run customer software.