Workload and network-optimized computing systems

  • Authors:

  • D. P. LaPotin;S. Daijavad;C. L. Johnson;S. W. Hunter;K. Ishizaki;H. Franke;H. D. Achilles;D. P. Dumarot;N. A. Greco;B. Davari

  • Affiliations:

  • IBM Research Division, Austin Research Laboratory, Austin, TX;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, NY;IBM Research Division, Rochester, MN;IBM Research, Research Triangle Park, NC;IBM Research Division, IBM Tokyo Research Laboratory, Kanagawa, Japan;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, NY;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, NY;IBM Systems and Technology Group, Integrated Systems Development, Poughkeepsie, NY;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, NY;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, NY

  • Venue:
  • IBM Journal of Research and Development
  • Year:
  • 2010

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Abstract

This paper describes a recent system-level trend toward the use of massive on-chip parallelism combined with efficient hardware accelerators and integrated networking to enable new classes of applications and computing-systems functionality. This system transition is driven by semiconductor physics and emerging network-application requirements. In contrast to general-purpose approaches, workload and network-optimized computing provides significant cost, performance, and power advantages relative to historical frequency-scaling approaches in a serial computational model. We highlight the advantages of on-chip network optimization that enables efficient computation and new services at the network edge of the data center. Software and application development challenges are presented, and a service-oriented architecture application example is shown that characterizes the power and performance advantages for these systems. We also discuss a roadmap for next-generation systems that proportionally scale with future networking bandwidth growth rates and employ 3-D chip integration methods for design flexibility and modularity.