Reliability-Availability-Serviceability Characteristics of a Compressed-Memory System
DSN '00 Proceedings of the 2000 International Conference on Dependable Systems and Networks (formerly FTCS-30 and DCCA-8)
Parallel compression with cooperative dictionary construction
DCC '96 Proceedings of the Conference on Data Compression
Exploiting prolific types for memory management and optimizations
POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Cache-Memory Interfaces in Compressed Memory Systems
IEEE Transactions on Computers
The performance advantage of applying compression to the memory system
Proceedings of the 2002 workshop on Memory system performance
Memory resource management in VMware ESX server
ACM SIGOPS Operating Systems Review - OSDI '02: Proceedings of the 5th symposium on Operating systems design and implementation
A "flight data recorder" for enabling full-system multiprocessor deterministic replay
Proceedings of the 30th annual international symposium on Computer architecture
Improving 64-Bit Java IPF Performance by Compressing Heap References
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Adaptive Cache Compression for High-Performance Processors
Proceedings of the 31st annual international symposium on Computer architecture
Selective main memory compression by identifying program phase changes
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
Memory resource management in VMware ESX server
OSDI '02 Proceedings of the 5th symposium on Operating systems design and implementationCopyright restrictions prevent ACM from being able to make the PDFs for this conference available for downloading
A Robust Main-Memory Compression Scheme
Proceedings of the 32nd annual international symposium on Computer Architecture
CRAMES: compressed RAM for embedded systems
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Memory State Compressors for Giga-Scale Checkpoint/Restore
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
High-performance operating system controlled memory compression
Proceedings of the 43rd annual Design Automation Conference
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Resource management architecture for future information appliances
Journal of Embedded Computing - Real-Time and Embedded Computing Systems
Proceedings of the 21st annual international conference on Supercomputing
Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Quasistatic shared libraries and XIP for memory footprint reduction in MMU-less embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Stateful hardware decompression in networking environment
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
MEMMU: Memory expansion for MMU-less embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Joint source-cryptographic-channel coding for dependable systems
International Journal of Computer Applications in Technology
Energy and performance evaluation of lossless file data compression on server systems
SYSTOR '09 Proceedings of SYSTOR 2009: The Israeli Experimental Systems Conference
Algorithms and data structures for compressed-memory machines
IBM Journal of Research and Development
On internal organization in compressed random-access memories
IBM Journal of Research and Development
Memory expansion technology (MXT): competitive impact
IBM Journal of Research and Development
Online memory compression for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
High-performance operating system controlled online memory compression
ACM Transactions on Embedded Computing Systems (TECS)
Cache aware compression for processor debug support
Proceedings of the Conference on Design, Automation and Test in Europe
Decoupled zero-compressed memory
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
C-pack: a high-performance microprocessor cache compression algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance of SAP ERP with memory virtualization using IBM active memory expansion as an example
Proceedings of the 5th international workshop on Virtualization technologies in distributed computing
Value compression for efficient computation
Euro-Par'05 Proceedings of the 11th international Euro-Par conference on Parallel Processing
Delta-compressed caching for overcoming the write bandwidth limitation of hybrid main memory
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
A survey of architectural techniques for DRAM power management
International Journal of High Performance Systems Architecture
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
Decoupled compressed cache: exploiting spatial locality for energy-optimized compressed caching
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
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Several technologies are leveraged to establish an architecture for a low-cost, high-performance memory controller and memory system that more than double the effective size of the installed main memory without significant added cost. This architecture is the first of its kind to employ real-time main-memory content compression at a performance competitive with the best the market has to offer. A large low-latency shared cache exists between the processor bus and a content-compressed main memory. Highspeed, low-latency hardware performs realtime compression and decompression of data traffic between the shared cache and the main memory. Sophisticated memory management hardware dynamically allocates main-memory storage in small sectors to accommodate storing the variable-sized compressed data without the need for "garbage" collection or significant wasted space due to fragmentation. Though the main-memory compression ratio is limited to the range 1:1-64:1, typical ratios range between 2:1 and 6:1, as measured in "real-world" system applications.