Code compression for embedded systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
A Low-Power CAM Design for LZ Data Compression
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems
Data Compression Transformations for Dynamically Allocated Data Structures
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Automatic generation of breakpoint hardware for silicon debug
Proceedings of the 41st annual Design Automation Conference
Adaptive Cache Compression for High-Performance Processors
Proceedings of the 31st annual international symposium on Computer architecture
CRAMES: compressed RAM for embedded systems
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Compressing Functional Tests for Microprocessors
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Modified Pseudo LRU Replacement Algorithm
ECBS '06 Proceedings of the 13th Annual IEEE International Symposium and Workshop on Engineering of Computer Based Systems
Interactive presentation: Low cost debug architecture using lossy compression for silicon debug
Proceedings of the conference on Design, automation and test in Europe
CacheCompress: a novel approach for test data compression with cache for IP embedded cores
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
IBM memory expansion technology (MXT)
IBM Journal of Research and Development
Online cache state dumping for processor debug
Proceedings of the 46th Annual Design Automation Conference
On signal tracing in post-silicon validation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug
Proceedings of the 49th Annual Design Automation Conference
Post-silicon platform for the functional diagnosis and debug of networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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During post-silicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, the bulk of which is composed of cache, the problem is essentially that of transferring cache contents off-chip, to a logic analyzer. In order to reduce the transfer time and save expensive logic analyzer memory, we propose to compress the cache contents on their way out. We present a hardware compression engine for cache data using a Cache Aware Compression strategy that exploits knowledge of the cache fields and their behavior to achieve an effective compression. Experimental results indicate that the technique results in 7--31% better compression than one that treats the data as just one long bit stream. We also describe and evaluate a parallel compression architecture that uses multiple compression engines, resulting in a 54% reduction in transfer time.