Test Data Compression Using Dictionaries with Fixed-Length Indices
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Multiscan-Based Test Compression and Hardware Decompression Using LZ77
ITC '02 Proceedings of the 2002 IEEE International Test Conference
IEEE Transactions on Computers
Synchronization overhead in SOC compressed test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DATA COMPRESSION FOR MULTIPLE SCAN CHAINS USING DICTIONARIES WITH CORRECTIONS
ITC '04 Proceedings of the International Test Conference on International Test Conference
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Online cache state dumping for processor debug
Proceedings of the 46th Annual Design Automation Conference
Cache aware compression for processor debug support
Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we propose a novel test data compression technique named CacheCompress, which combines selective encoding and dynamic dictionary based encoding. Depending on the number of specified bits, a test data word is either encoded in a single code word or as a lookup in the dictionary. Explicit dictionary initialization is not required since the content of the dictionary is updated during testing. The dictionary itself only contains the most recently used patterns, thus it exhibits a behaviour similar to a cache. Experiments show that our technique achieves higher compression ratio than other recent compression schemes while the dictionary size has been dramatically reduced.