Proceedings of the conference on Design, automation and test in Europe - Volume 2
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Combining dictionary coding and LFSR reseeding for test data compression
Proceedings of the 41st annual Design Automation Conference
Test data compression technique using selective don't-care identification
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Hybrid BIST Based on Repeating Sequences and Cluster Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Using MUXs Network to Hide Bunches of Scan Chains
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Synchronization overhead in SOC compressed test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using the Nonlinear Property of FSR and Dictionary Coding for Reduction of Test Volume
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Frugal linear network-based test decompression for drastic test cost reductions
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A Huffman-based coding with efficient test application
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
On test data compression using selective don't-care identification
Journal of Computer Science and Technology
Test data compression scheme based on variable-to-fixed-plus-variable-length coding
Journal of Systems Architecture: the EUROMICRO Journal
CacheCompress: a novel approach for test data compression with cache for IP embedded cores
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Scan Test Response Compaction Combined with Diagnosis Capabilities
Journal of Electronic Testing: Theory and Applications
A Variable-Length Coding Adjustable for Compressed Test Application
IEICE - Transactions on Information and Systems
Computers and Electrical Engineering
Time-multiplexed compressed test of SOC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On reducing test power and test volume by selective pattern compression schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression based on geometric shapes
Computers and Electrical Engineering
A new scheme of test data compression based on equal-run-length coding (ERLC)
Integration, the VLSI Journal
COMPAS – compressed test pattern sequencer for scan based circuits
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
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Localized delay defects, like resistive shorts, resistiveopens, etc., can be effectively detected by testing the longesttestable path through each wire (or gate) in the circuit. Sucha delay test set is referred to as a longest-path-per-wire testset. ...