HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Using a single input to support multiple scan chains
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
Test application time and volume compression through seed overlapping
Proceedings of the 40th annual Design Automation Conference
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Virtual Scan Chains: A Means for Reducing Scan Length in Cores
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Test Data Compression Using Dictionaries with Fixed-Length Indices
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A Reconfigurable Shared Scan-in Architecture
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Reducing Test Application Time Through Test Data Mutation Encoding
Proceedings of the conference on Design, automation and test in Europe
On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Changing the Scan Enable during Shift
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Combining dictionary coding and LFSR reseeding for test data compression
Proceedings of the 41st annual Design Automation Conference
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction
ITC '04 Proceedings of the International Test Conference on International Test Conference
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test set embedding for deterministic BIST using a reconfigurable interconnection network
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a decompression architecture using a periodically alterable MUX network. Compared to static XORs network, the periodically alterable MUXs network has multiple configurations to decode the input information flexibly. Probability analysis can help us to select the proper parameter when considering the DFT schemes. With the dedicated efforts, the smaller test data volume and test application time can be achieved compared to previous techniques.