Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture

Authors:
Manish Sharma;Janak H. Patel;Jeff Rearick
Affiliations:
-;-;-
Venue:
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Year:
2003

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Abstract

Localized delay defects, like resistive shorts, resistiveopens, etc., can be effectively detected by testing the longesttestable path through each wire (or gate) in the circuit. Sucha delay test set is referred to as a longest-path-per-wire testset. In this paper we study test data volume and test applicationtime reduction techniques for such tests based on theIllinois Scan architecture. We present a novel ATPG flowto quickly determine longest-path-per-wire test sets underconstraints imposed by the Illinois scan architecture. Resultsof experiments on ISCAS sequential circuits are presented.On an average we achieve a test data volume reductionof 2.79X and number of test cycles reduction of 3.28Xfor robust path delay tests (as compared to the case withoutIllinois scan). The corresponding numbers for non-robusttests are 3.58X and 4.24X.