Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
OPMISR: the foundation for compressed ATPG vectors
Proceedings of the IEEE International Test Conference 2001
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Virtual Scan Chains: A Means for Reducing Scan Length in Cores
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A Reconfigurable Shared Scan-in Architecture
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Using MUXs Network to Hide Bunches of Scan Chains
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
XPAND: An Efficient Test Stimulus Compression Technique
IEEE Transactions on Computers
Survey of Test Vector Compression Techniques
IEEE Design & Test
Test generation in the presence of timing exceptions and constraints
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Electronic Testing: Theory and Applications
Reducing test application time, test data volume and test power through Virtual Chain Partition
Integration, the VLSI Journal
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Scan cell positioning for boosting the compression of fan-out networks
Journal of Computer Science and Technology - Special section on trust and reputation management in future computing systmes and applications
Low-power test in compression-based reconfigurable scan architectures
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
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This paper extends the Reconfigurable Shared Scan-inarchitecture (RSSA) to provide additional ability to changevalues on the scan configuration signals (scan enablesignals) during the scan operation on a per-shift basis. Weshow that the extra flexibility of reconfiguring the scanchains every shift cycle reduces the number of differentconfigurations required by RSSA while keeping test coveragethe same. In addition a simpler analysis can be used toconstruct the scan chains.This is the first paper of its kind that treats the ScanEnable signal as a test data signal during the scan operationof a test pattern. Results are presented on some ISCAS aswell as industrial circuits.