Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
A Reconfigurable Shared Scan-in Architecture
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Embedded Deterministic Test for Low-Cost Manufacturing
IEEE Design & Test
Changing the Scan Enable during Shift
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
XPAND: An Efficient Test Stimulus Compression Technique
IEEE Transactions on Computers
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction
ITC '04 Proceedings of the International Test Conference on International Test Conference
Survey of Test Vector Compression Techniques
IEEE Design & Test
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While integrated circuits of ever increasing size and complexity necessitate larger test sets for ensuring high test quality, the consequent test time and data volume reflect into elevated test costs. Test data compression solutions have been proposed to address this problem by storing and delivering stimuli in a compressed format. The effectiveness of these techniques, however, strongly relies on the distribution of the specified bits of test vectors. In this paper, we propose a scan cell partitioning technique so as to ensure that specified bits are uniformly distributed across the scan slices, especially for the test vectors with higher density of specified bits. The proposed scan cell partitioning process is driven by an integer linear programming (ILP) formulation, wherein it is also possible to account for the layout and routing constraints. While the proposed technique can be applied to increase the effectiveness of any combinational decompression architecture, in this paper, we present its application in conjunction with a fan-out based decompression architecture. The experimental results also confirm the compression enhancement of the proposed methodology.