Embedded Deterministic Test for Low-Cost Manufacturing

Authors:
Janusz Rajski;Mark Kassab;Nilanjan Mukherjee;Nagesh Tamarapalli;Jerzy Tyszer;Jun Qian
Affiliations:
-;-;-;-;-;-
Venue:
IEEE Design & Test
Year:
2003

Citing 11
Cited 6

Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers

IEEE Transactions on Computers - Special issue on fault-tolerant computing
Test volume and application time reduction through scan chain concealment

Proceedings of the 38th annual Design Automation Conference
Tailoring ATPG for embedded testing

Proceedings of the IEEE International Test Conference 2001
Two-dimensional test data compression for scan-based deterministic BIST

Proceedings of the IEEE International Test Conference 2001
OPMISR: the foundation for compressed ATPG vectors

Proceedings of the IEEE International Test Conference 2001
Test vector encoding using partial LFSR reseeding

Proceedings of the IEEE International Test Conference 2001
Scan Vector Compression/Decompression Using Statistical Coding

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators

VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
High Speed Ring Generators and Compactors of Test Data

VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Embedded Deterministic Test for Low-Cost Manufacturing Test

ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding

ATS '01 Proceedings of the 10th Asian Test Symposium

Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells

Journal of Electronic Testing: Theory and Applications
Compacting test vector sets via strategic use of implications

Proceedings of the 2009 International Conference on Computer-Aided Design
Scan cell positioning for boosting the compression of fan-out networks

Journal of Computer Science and Technology - Special section on trust and reputation management in future computing systmes and applications
Reducing the storage requirements of a test sequence by using a background vector

Proceedings of the Conference on Design, Automation and Test in Europe
Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping

Journal of Electronic Testing: Theory and Applications
Diagnosis of logic circuits using compressed deterministic data and on-chip response comparison

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

Editor's note: You have probably heard that BIST takes too long and its fault coverage is low, and that deterministic test requires too many patterns. This article shows how on-chip compression and decompression techniques can provide high fault coverage with low test times.驴Rob Aitken, Artisan Components