Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Power Driven Chaining of Flip-Flops in Scan Architectures
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing
IEEE Design & Test
Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
A routability constrained scan chain ordering technique for test power reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction
IEEE Transactions on Computers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation and clock disabling for simultaneous test time and power reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LT-RTPG: a new test-per-scan BIST TPG for low switching activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
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In order to further reduce test data storage and test power of deterministic BIST based on scan slice overlapping, this paper proposes a novel optimization approach. Firstly, a san cell grouping method considering layout constraint is introduced to shorten the scan chain. Secondly, a novel scan cell ordering approach considering layout constraint is proposed to optimize the order of scan chain. Lastly, the authors propose an improved test pattern partition algorithm which selects the scan slice with the most specified bits as the first scan slice of the current overlapping block. Experimental results indicate that the proposed optimization approach significantly reduces the scan-in transitions and test data storage by 73%---93% and 60%---87%, respectively.