New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
A BIST TPG for low power dissipation and high fault coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST
IEICE - Transactions on Information and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LPTest: a Flexible Low-Power Test Pattern Generator
Journal of Electronic Testing: Theory and Applications
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping
Journal of Electronic Testing: Theory and Applications
Test patterns of multiple SIC vectors: theory and application in BIST schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A new built-in self-test (BIST) test pattern generator (TPG) design, called low-transition random TPG (LT-RTPG), is presented. An LT-RTPG is composed of a linear feedback shift register (LFSR), a κ-input AND gate, and a T flip-flop. When used to generate test patterns for test-per-scan BIST, it decreases the number of transitions that occur during scan shifting and, hence, decreases switching activity during testing. Various properties of LT-RTPGs are identified and a methodology for their design is presented. Experimental results demonstrate that LT-RTPGs designed using the proposed methodology decrease switching activity during BIST by significant amounts while providing high fault coverage.