Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
IEEE Transactions on Computers
An analysis of power reduction techniques in scan testing
Proceedings of the IEEE International Test Conference 2001
A Reseeding Technique for LFSR-Based BIST Applications
ATS '02 Proceedings of the 11th Asian Test Symposium
A Technique to Reduce Power and Test Application Time in BIST
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
LT-RTPG: a new test-per-scan BIST TPG for low switching activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a new low power BIST TPG scheme for reducing scan transitions. It uses a transition freezing and melting method which is implemented of the transition freezing block and a MUX. When random test patterns are generated from an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique freezes transitions of patterns using a freezing value. Experimental results show that the proposed BIST TPG schemes can reduce average power reduction by about 60% without performance loss and peak power by about 30% in ISCAS'89 benchmark circuits.