Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST
IEICE - Transactions on Information and Systems
Fully X-tolerant, very high scan compression
Proceedings of the 47th Design Automation Conference
| Hi-index | 0.00 |
In this paper we describe a new design methodology for LFSR-based test pattern generators (TPG).Multiple seed are produced by the TPG itself to deal with hard-to-detect faults, and this function is achieved without using a ROM to store the seeds.A reseedling logic is incorporated in the TPG, which loads new seeds into the LFSR whenever specific states are reached.In this way, useless test vectors are skipped and thus the test application time can be greatly reduced.We experiment the design methodology by applying it to some MCNC benchmark circuits, and the results show that TPGs designed with this technique require much less hardware overhead than the previous known reseedling techniques.Keywords:Reseedling, LFST, Pseudo-Random Testing, Test Pattern Generator, BIST