Condensed Linear Feedback Shift Register (LFSR) Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers - The MIT Press scientific computation series
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Linear Feedback Shift Register Design Using Cyclic Codes
IEEE Transactions on Computers
Digital signal processing in VLSI
Digital signal processing in VLSI
Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
Recursive Pseudoexhaustive Test Pattern Generation
IEEE Transactions on Computers
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
Exhaustive Test Pattern Generation Using Cyclic Codes
IEEE Transactions on Computers
Test pattern generation based on arithmetic operations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Testability Enhancement for Control-Flow Intensive Behaviors
Journal of Electronic Testing: Theory and Applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An Accumulator-Based BIST Approach for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications
Optimal hardware pattern generation for functional BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On applying the set covering model to reseeding
Proceedings of the conference on Design, automation and test in Europe
A novel reseeding technique for accumulator-based test pattern generation
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Testing Schemes for FIR Filter Structures
IEEE Transactions on Computers
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
Journal of Electronic Testing: Theory and Applications
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Non-Intrusive BIST for Systems-on-a-Chip
ITC '00 Proceedings of the 2000 IEEE International Test Conference
BISTing Data Paths at Behavioral Level
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Parameterizable Testing Scheme for FIR Filters
ITC '97 Proceedings of the 1997 IEEE International Test Conference
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
BIST Technique by Equally Spaced Test Vector Sequences
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Test Vector Embedding into Accumulator-Generated Sequences: A Linear-Time Solution
IEEE Transactions on Computers
A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST
IEICE - Transactions on Information and Systems
Recursive pseudo-exhaustive two-pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient architecture for accumulator-based test generation of SIC pairs
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Built-in functional tests for silicon validation and system integration of telecom SoC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Electronic Testing: Theory and Applications
Antirandom Test Vectors for BIST in Hardware/Software Systems
Fundamenta Informaticae
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Existing built-in self-test (BIST) strategies require the use of specialized test pattern generation hardware which introduces significant area overhead and performance degradation. In this paper, we propose an entirely new approach to generate test patterns. The method is based on adders widely available in data-path architectures used in digital signal processing circuits and general purpose processors. The resultant test patterns, generated by continuously accumulating a constant value, provide a complete state coverage on subspaces of contiguous bits. This new test generation scheme, along with the recently introduced accumulator-based compaction scheme [19] facilitates a BIST strategy for high performance datapath architectures that uses the functionality of existing hardware, is entirely integrated with the circuit under test, and results in at-speed testing with no performance degradation and no area overhead.