Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
IEEE Transactions on Computers
Structured Design-for-Debug - The SuperSPARCTM II Methodology and Implementation
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A New Hardware Fault Insertion Scheme for System Diagnostics Verification
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
FRITS " A Microprocessor Functional BIST Method
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Visibility enhancement for silicon debug
Proceedings of the 43rd annual Design Automation Conference
Functional Debug Techniques for Embedded Systems
IEEE Design & Test
In-System Silicon Validation and Debug
IEEE Design & Test
Scan-based BIST fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testing ASICs with multiple identical cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 50th Annual Design Automation Conference
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Existing silicon validation techniques only address test data capture issues. They all assume the existence of live traffic in the system. Unfortunately, this is not always the case in real life. This paper proposes a novel design methodology for silicon validation and system integration. It uses built-in functional tests to simulate live traffic at full speed when a real one is not available at the arrival of the first silicon. The proposed methodology provides a platform upon which many silicon validation and system integration tasks can be performed before a real traffic is ready. It can also be used to cover logic corner cases that may not be easily achievable in real life. The proposed methodology has been proven effective on time-to-market and quality of verification with multiple complex system-on-chip designs.