Interconnection fabric design for tracing signals in post-silicon validation
Proceedings of the 46th Annual Design Automation Conference
Masking timing errors on speed-paths in logic circuits
Proceedings of the Conference on Design, Automation and Test in Europe
On signal tracing in post-silicon validation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Built-in functional tests for silicon validation and system integration of telecom SoC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug
Proceedings of the 49th Annual Design Automation Conference
Microprocessors & Microsystems
Proceedings of the 50th Annual Design Automation Conference
A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Post-silicon platform for the functional diagnosis and debug of networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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First-silicon validation and debug require a labor-intensive engineering effort of several months and have become the least predictable and most time-consuming part of a new 90-nm chip's development cycle. Lack of adequate tools and automatic procedures is a big factor in this bottleneck. Other difficulties include nondeterministic operation and lack of time-specific expected values. This article presents a new approach that provides an efficient scalable solution to overcome these difficulties. The end results are a significant reduction of the silicon validation and debug time, and faster discovery and root-cause determination of integration problems, design bugs, and chip defects.