ITC '99 Proceedings of the 1999 IEEE International Test Conference
X-Tolerant Test Response Compaction
IEEE Design & Test
Response shaper: a novel technique to enhance unknown tolerance for output response compaction
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Interactive presentation: Low cost debug architecture using lossy compression for silicon debug
Proceedings of the conference on Design, automation and test in Europe
A multi-core debug platform for NoC-based systems
Proceedings of the conference on Design, automation and test in Europe
Fixing Design Errors with Counterexamples and Resynthesis
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
In-System Silicon Validation and Debug
IEEE Design & Test
IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors
Proceedings of the 45th annual Design Automation Conference
Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Proceedings of the conference on Design, automation and test in Europe
Enhancing Silicon Debug via Periodic Monitoring
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Automated Selection of Signals to Observe for Efficient Silicon Debug
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
A trace-capable instruction cache for cost efficient real-time program trace compression in SoC
Proceedings of the 46th Annual Design Automation Conference
Interconnection fabric design for tracing signals in post-silicon validation
Proceedings of the 46th Annual Design Automation Conference
Cache aware compression for processor debug support
Proceedings of the Conference on Design, Automation and Test in Europe
Trace signal selection for visibility enhancement in post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
On signal tracing in post-silicon validation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Trace Buffer-Based Silicon Debug with Lossless Compression
VLSID '11 Proceedings of the 2011 24th International Conference on VLSI Design
| Hi-index | 0.00 |
The effectiveness of at-speed silicon debug is constrained by the limited trace buffer size and/or trace port bandwidth, requiring highly-efficient trace data compression solutions. As it is usually inevitable to have unknown 'X' values during silicon debug, trace compressor should be equipped with X-tolerance feature in order not to significantly degrade error detection capability. To tackle this problem, this paper presents a novel reconfigurable X-tolerant trace compressor, namely X-Tracer, which is able to tolerate as many X-bits as possible in the trace streams while guaranteeing high compression ratio, at the cost of little extra design-for-debug hardware. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique.