Automating post-silicon debugging and repair
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Optimizing non-monotonic interconnect using functional simulation and logic restructuring
Proceedings of the 2008 international symposium on Physical design
Using unsatisfiable cores to debug multiple design errors
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Scalable don't-care-based logic optimization and resynthesis
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Debugging strategies for mere mortals
Proceedings of the 46th Annual Design Automation Conference
Increasing the accuracy of SAT-based debugging
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Scalable don't-care-based logic optimization and resynthesis
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Journal of Computer and System Sciences
A robust functional ECO engine by SAT proof minimization and interpolation techniques
Proceedings of the International Conference on Computer-Aided Design
Automated error localization and correction for imperative programs
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug
Proceedings of the 49th Annual Design Automation Conference
Generalized SAT-sweeping for post-mapping optimization
Proceedings of the 49th Annual Design Automation Conference
Automated design debugging in a testbench-based verification environment
Microprocessors & Microsystems
Intuitive ECO synthesis for high performance circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Repair with on-the-fly program analysis
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
FoREnSiC: an automatic debugging environment for C programs
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
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In this work we propose a new error-correction framework, called CoRe, which uses counterexamples, or bug traces, generated in verification to automatically correct errors in digital designs. CoRe is powered by two innovative resynthesis techniques, goal-directed search (GDS) and entropy-guided search (EGS), which modify the functionality of internal circuit's nodes to match the desired specification. We evaluate our solution to designs and errors arising during combinational equivalence-checking, as well as simulation-based verification of digital systems. Compared with previously proposed techniques, CoRe is more powerful in that: (1) it can fix a broader range of error types because it does not rely on specific error models; (2) it derives the correct functionality from simulation vectors, hence not requiring golden netlists; and (3) it can be applied to a range of verification flows, including formal and simulation-based.