Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
Simplifying failure-inducing input
Proceedings of the 2000 ACM SIGSOFT international symposium on Software testing and analysis
System-on-a-chip verification: methodology and techniques
System-on-a-chip verification: methodology and techniques
A hybrid verification approach: getting deep into the design
Proceedings of the 39th annual Design Automation Conference
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Writing Testbenches: Functional Verification of HDL Models, Second Edition
Writing Testbenches: Functional Verification of HDL Models, Second Edition
Design diagnosis using Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Debugging Sequential Circuits Using Boolean Satisfiability
MTV '04 Proceedings of the Fifth International Workshop on Microprocessor Test and Verification
Algorithms for compacting error traces
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Post-verification debugging of hierarchical designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Engineering trust with semantic guardians
Proceedings of the conference on Design, automation and test in Europe
Fixing Design Errors with Counterexamples and Resynthesis
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Automating Logic Rectification by Approximate SPFDs
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Automatic error diagnosis and correction for RTL designs
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
Automatic fault localization for property checking
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
Design error diagnosis and correction via test vector simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simulation-Based Bug Trace Minimization With BMC-Based Refinement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic Fault Localization for Property Checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Recent improvements in design verification strive to automate error detection and greatly enhance engineers' ability to detect functional errors. However, the process of diagnosing the cause of these errors, and subsequently fixing them, remains one of the most difficult tasks of verification. The complexity of design descriptions, paired with the scarcity of software tools supporting this task lead to an activity that is mostly ad-hoc, labor intensive and accessible only to a few debugging specialists within a design house. This paper discusses some recent research solutions that support the debugging effort by simplifying and automating bug diagnosis. These novel techniques demonstrate that, through the support of structured methodologies, debugging can become a task pursued by the average design engineer. We also outline some of the upcoming trends in design verification, postponing some the verification effort to runtime, and discuss how debugging could leverage these trends to achieve better quality of results.