Exact calculation of synchronization sequences based on binary decision diagrams
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Symbolic guided search for CTL model checking
Proceedings of the 37th Annual Design Automation Conference
Formal property verification by abstraction refinement with formal, simulation and hybrid engines
Proceedings of the 38th annual Design Automation Conference
Symbolic Model Checking
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On Combining Formal and Informal Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Symbolic Trajectory Evaluation
Formal Hardware Verification - Methods and Systems in Comparison
Combination Model Checking: Approach and a Case Study
Proceedings of the 19th IEEE international conference on Automated software engineering
Simulation-based bug trace minimization with BMC-based refinement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Distance-guided hybrid verification with GUIDO
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Guiding simulation with increasingly refined abstract traces
Proceedings of the 43rd annual Design Automation Conference
A novel collaborative scheme of simulation and model checking for system properties verification
Computers in Industry - Special issue: Collaborative environments for concurrent engineering
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
Fifteen Years of Formal Property Verification in Intel
25 Years of Model Checking
Debugging strategies for mere mortals
Proceedings of the 46th Annual Design Automation Conference
Under-approximation Heuristics for Grid-based Bounded Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Finding reset nondeterminism in RTL designs: scalable X-analysis methodology and case study
Proceedings of the Conference on Design, Automation and Test in Europe
Model optimization techniques in a verification platform for classified properties
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
High level reduction technique for multiway decision graphs based model checking
VECoS'07 Proceedings of the First international conference on Verification and Evaluation of Computer and Communication Systems
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One method of handling the computational complexity of the verification process is to combine the strengths of different approaches. We propose a hybrid verification technology combining symbolic trajectory evaluation with either symbolic model checking or SAT-based model checking. This reduces significantly the cost (both human and computing) of verifying circuits with complex initialisation, as well as simplifying proof development by enhancing verification productivity. The approach has been tested on current Intel designs.