In transition from global to modular temporal reasoning about programs
Logics and models of concurrent systems
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
Adaptive variable reordering for symbolic model checking
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A hybrid verification approach: getting deep into the design
Proceedings of the 39th annual Design Automation Conference
Input Elimination and Abstraction in Model Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking Visualization
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
The ForSpec Temporal Logic: A New Temporal Property-Specification Language
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Automatic Datapath Extraction for Efficient Usage of HDD
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Prioritized Traversal: Efficient Reachability Analysis for Verification and Falsification
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Benefits of Bounded Model Checking at an Industrial Setting
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Formal Verification of Digital Circuits Using Symbolic Ternary System Models
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Another Look at LTL Model Checking
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent?
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Formal verification coverage: computing the coverage gap between temporal specifications
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Verifying very large industrial circuits using 100 processes and beyond
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Formal verification of backward compatibility of microcode
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
The theory and practice of SALT
NFM'11 Proceedings of the Third international conference on NASA Formal methods
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Model checking technologies have been applied to hardware verification in the last 15 years. Pioneering work has been conducted in Intel since 1990 using model checking technologies to build industrial hardware verification systems. This paper reviews the evolution and the success of these systems in Intel and in particular it summarizes the many challenges and learning that have resulted from changing how hardware validation is performed in Intel to include formal property verification. The paper ends with a discussion on how the learning from hardware verification can be used to accelerate the industrial deployment of model-checking technologies for software verification.