Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model

Authors:
Sayantan Das;Ansuman Banerjee;Prasenjit Basu;Pallab Dasgupta;P. P. Chakrabarti;Chunduri Rama Mohan;Limor Fix
Affiliations:
Indian Institute of Technology-Kharagpur;Indian Institute of Technology-Kharagpur;Indian Institute of Technology-Kharagpur;Indian Institute of Technology-Kharagpur;Indian Institute of Technology-Kharagpur;Intel Corporation;Intel Corporation
Venue:
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Year:
2005

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Abstract

One of the emerging challenges in formal propertyverification (FPV) technology is the problem of deciding whether sufficient properties have been written to cover the design intent. Existing literature on FPV coverage does not solve this problem adequately, since they primarily analyze the coverage of a specification against a given implementation. On the other hand, we consider the task of determining the coverage of a formal specification against a high-level fault model that is independent of any specific implementation. We show that such a coverage analysis discovers behavioral gaps in the specification and prompts the design architect to add more properties to close the behavioral gaps. Our results establish that the coverage analysis task at this level is computationally complex, but it is possible to obtain a conservative estimate of the coverage at low cost.