IEEE Spectrum
Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
System-on-a-chip verification: methodology and techniques
System-on-a-chip verification: methodology and techniques
The Verilog PLI Handbook
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
A Practical Approach to Coverage in Model Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
A generic micro-architectural test plan approach for microprocessor verification
Proceedings of the 42nd annual Design Automation Conference
A Roadmap for Formal Property Verification
A Roadmap for Formal Property Verification
Cohesive Coverage Management for Simulation and Formal Property Verification
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Design intent coverage revisited
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Inline Assertions - Embedding Formal Properties in a Test Bench
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Functional Verification Coverage Measurement and Analysis
Functional Verification Coverage Measurement and Analysis
Coverage Management with Inline Assertions and Formal Test Points
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
Cohesive Coverage Management Leveraging Formal Test Plans: A Design Intent Verification Perspective
Cohesive Coverage Management Leveraging Formal Test Plans: A Design Intent Verification Perspective
Design-Intent Coverage—A New Paradigm for Formal Property Verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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It has been advocated by many experts in design verification that the key to successful verification convergence lies in developing the verification plan with adequate formal rigor. Traditionally, the verification plans for simulation and formal property verification (FPV) are developed in different ways, using different formalisms, and with different coverage goals. In this paper, we propose a framework where the difference between formal properties and simulation test points is diluted by using methods for translating one form of the specification to the other. This allows us to reuse simulation coverage to facilitate formal verification and to reuse proven formal properties to cover simulation test points. We also propose the use of inline assertions in procedural (possibly randomized) test benches, and show that it facilitates the use of hybrid verification techniques between simulation and bounded model checking. We propose the use of promising combinations of formal methods presented in our earlier papers to shape a hierarchical verification flow where simulation and formal methods aim to cover a common design intent specification. The proposed flow is demonstrated using a detailed case study of the ARM AMBA verification benchmark. We believe that the methods presented in this work will stimulate new thought processes and ultimately lead to wider adoption of cohesive coverage management techniques in the design intent validation flow.