Automatic test program generation for pipelined processors
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
User defined coverage—a tool supported methodology for design verification
DAC '98 Proceedings of the 35th annual Design Automation Conference
Functional verification methodology for microprocessors using the Genesys test-program generator
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Micro architecture coverage directed generation of test programs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Multiprocessing design verification methodology for Motorola MPC74XX PowerPC microprocessor
Proceedings of the 37th Annual Design Automation Conference
Semi-formal test generation with genevieve
Proceedings of the 38th annual Design Automation Conference
A new verification methodology for complex pipeline behavior
Proceedings of the 38th annual Design Automation Conference
Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Piparazzi: a test program generator for micro-architecture flow verification
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Practical methods in coverage-oriented verification of the merom microprocessor
Proceedings of the 43rd annual Design Automation Conference
Advanced Analysis Techniques for Cross-Product Coverage
IEEE Transactions on Computers
Automatic verification of external interrupt behaviors for microprocessor design
Proceedings of the 44th annual Design Automation Conference
Automatic constraint based test generation for behavioral HDL models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cohesive Coverage Management: Simulation Meets Formal Methods
Journal of Electronic Testing: Theory and Applications
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Modern microprocessors share several common types of micro-architectural building blocks. The rising complexity of the micro-architecture increases the risk of bugs and the difficulty of achieving comprehensive verification. We propose a methodology to exploit the commonality in the different microprocessors to create a design-independent micro-architectural test plan. Our method allows the testing of the huge micro-architectural test space by using systematic partitioning, which offers a high level of comprehensiveness of the tested behaviors. We show how this method was used to find bugs during verification of an actual high-end microprocessor. Our results show the advantages of this approach over the more traditional test methods that use design specific test plans or that use tools with little micro-architectural knowledge for covering micro-architectural aspects of the design.