Overview of PowerPCTM 620 Multiprocessor Verification Strategy
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A simulation-based method for the verification of shared memory in multiprocessor systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Stimuli Generation with Late Binding of Values
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A generic micro-architectural test plan approach for microprocessor verification
Proceedings of the 42nd annual Design Automation Conference
Piparazzi: a test program generator for micro-architecture flow verification
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Validating power architecture™ technology-based MPSoCs through executable specifications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Multiprocessing (MP) design verification has been one of the bottlenecks for high performance microprocessor design projects. The problem is getting worse as the design complexity increases and more cache structures are integrated into one single chip. The challenges that MP verification faces today include: huge chip/system simulation model sizes, long simulation cycles, relative inefficiency of the simulation tools compared to uniprocessor, and so on. To solve these challenging problems, we developed a new methodology and simulation flow for an upcoming design in Motorola's G4 generation of microprocessors, MPC74XX1. The key strategy of this methodology was to start MP verification as early as the design implementation started. The same methodology/tool set were first developed for MP verification at the unit level, then reused at the multiple-unit level, and eventually reused at the chip/system level. In this paper, we will present the details of this methodology, and demonstrate why it is effective and efficient in detecting the majority of the MP functional defects at an early stage of the design phase.