Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
User defined coverage—a tool supported methodology for design verification
DAC '98 Proceedings of the 35th annual Design Automation Conference
Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
Multiprocessing design verification methodology for Motorola MPC74XX PowerPC microprocessor
Proceedings of the 37th Annual Design Automation Conference
Improving coverage analysis and test generation for large designs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A new verification methodology for complex pipeline behavior
Proceedings of the 38th annual Design Automation Conference
X-Gen: a random test-case generator for systems and SoCs
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Piparazzi: a test program generator for micro-architecture flow verification
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
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Generating test-cases that reach corner cases in the design is one of the main challenges in the functional verification of complex designs. In this paper, we describe a new technique that increases the ability of test generators by delaying assignment of values in the generated stimuli, until these values are used in the design. This late-binding allows the generator to have a more accurate view of the state of the design, and thus it can better choose the correct values. Experimental results show that late-binding can significantly improve coverage, with a reasonable penalty in simulation time.