Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-level transformations for minimizing syntactic variances
DAC '93 Proceedings of the 30th international Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Verilog HDL: a guide to digital design and synthesis
Verilog HDL: a guide to digital design and synthesis
Functional vector generation for HDL models using linear programming and 3-satisfiability
DAC '98 Proceedings of the 35th annual Design Automation Conference
Test generation for Gigahertz processors using an automatic functional constraint extractor
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
Proceedings of the 37th Annual Design Automation Conference
LPSAT: a unified approach to RTL satisfiability
Proceedings of the conference on Design, automation and test in Europe
TAO: regular expression-based register-transfer level testability analysis and optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Constraint Slving for Test Case Generation
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Fast test generation for circuits with RTL and gate-level views
Proceedings of the IEEE International Test Conference 2001
CHEETA: Composition of Hierarchical Sequential Tests Using ATKET
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Testability Analysis and ATPG on Behavioral RT-Level VHDL
Proceedings of the IEEE International Test Conference
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
RT-level TPG Exploiting High-Level Synthesis Information
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Program Slicing for Hierarchical Test Generation
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Instruction-Based Self-Testing of Processor Cores
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Design Verification with e
Assertion-based automated functional vectors generation using constraint logic programming
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A Framework for Constrained Functional Verification
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A generic micro-architectural test plan approach for microprocessor verification
Proceedings of the 42nd annual Design Automation Conference
Software-based self-testing methodology for processor cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Functional vector generation for HDL models using linear programming and Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Satisfiability-based test generation for nonseparable RTL controller-datapath circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With the emergence of complex high-performance microprocessors, functional test generation has become a crucial design step. Constraint-based test generation is a well-studied directed behavioral level functional test generation paradigm. The paradigm involves conversion of a given circuit model into a set of constraints and employing constraint solvers to generate tests for it. However, automatic extraction of constraints from a given behavioral hardware design language (HDL) model remained a challenging open problem. This paper proposes an approach for automatic extraction of word-level model constraints from the behavioral verilog HDL description. The scenarios to be tested are also expressed as constraints. The model and the scenario constraints are solved together using an integer solver to arrive at the necessary functional test. The effectiveness of the approach is demonstrated by automatically generating the constraint models for: 1) an exclusive-shared-invalid multiprocessor cache coherency model and 2) the 16-bit DLX-architecture, from their respective Verilog-based behavioral models. Experimental results that generate test vectors for high level scenarios like pipeline hazards, cache miss, etc., spanning over multiple time-frames are presented.