Industrial experience with test generation languages for processor verification
Proceedings of the 41st annual Design Automation Conference
VLIW: a case study of parallelism verification
Proceedings of the 42nd annual Design Automation Conference
IEEE P1647 and P1800: Two approaches to standardization and language design
IEEE Design & Test
Scheduling-based test-case generation for verification of multimedia SoCs
Proceedings of the 43rd annual Design Automation Conference
Conservative aspect-orientated programming with the e language
Proceedings of the 6th international conference on Aspect-oriented software development
Automatic constraint based test generation for behavioral HDL models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
on the design of a formal debugger for system architecture
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Using linear programming techniques for scheduling-based random test-case generation
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
Hi-index | 0.00 |
Design Verification with eSamir PalnitkarWritten for both experienced and new users, DesignVerification with e gives you a broadcoverage of e. It stresses the practical verification perspective of e rather than emphasizing only itslanguage aspects.This book- Introduces you to e-based verification methodologies Describes e syntax in detail, including structs, units, methods, events, temporal expressions.ï戮 and TCMs Explains the concepts of automatic generation, checking and coverage Discusses the e Reuse Methodology Describes essential topics such as coverage driven verification, e verification components (eVCs), and interfacing with C/C++ Illustrates a complete verification example in e Contains a quick-reference guide to the e language Offers many practical verification tipsIncludes overï戮 250 illustrations, examples, andexercises, and a verification resource list. Learning objectives and summariesare provided for each chapter.“Mr. Palnitkar illustrates how and why the power ofthe everification language and the underlying Specman Elite testbench automationtool are used to develop today's most advanced verification environments. Thisbook is valuable to both the novice and the experienced e user. I highlyrecommend it to anyone exploring functional verification”-Moshe GavrielovChief Executive OfficerVerisity Design, Inc.“This book demonstratesï戮 how e can be usedï戮 to createstate-of-the-art verification environments. An ideal bookï戮 to jumpstartaï戮 beginner and a handy reference for experts”-Rakesh DodejaEngineering ManagerIntel Corporation“The book gives a simple, logical, and well-organizedpresentation of ewith plenty of illustrations. This makes it an ideal text book for universitycourses on functionalï戮 verification”-Dr. Steven Levitanï戮 Professorï戮 Department of Electrical Engineeringï戮 University of Pittsburgh, Pittsburgh, PA“This book is ideal for readers with little or no e programming experience. It gives the reader athorough and practical understanding of not only the e language, butï戮 also how to effectively use thislanguage to develop complex functional verification environments.”-Bill SchubertVerification EngineerST Microelectronics, Inc.“The flow of the book is logical and gradual. Plentyof illustrations and examples makes this an ideal book for e users. A must-have for both beginners andexperts”-Karun MenonStaff EngineerSun Microsystems, Inc.PRENTICEHALLProfessionalTechnical ReferenceUpperSaddle River, NJï戮 07458www.phptr.comISBN:0-13-144309-0