Superlog, a unified design language for system-on-chip
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Art of Verification with VERA
Design Verification with e
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Verification is currently the hot topic in EDA. The move to deep-submicron feature sizes in the latest IC designs has caused a paradigm shift, moving the emphasis from design to verification. Designers must create ICs with upwards of 50 million equivalent gates and still meet cost and time-to-market constraints. To do this, they are limiting new logic to a minimum and relying heavily on the reuse of existing functional blocks and embedded memory to create the required chip functionality. This trend puts even more pressure on the already difficult problem of verifying these massive chips. To cope with these increased demands, chip designers, and therefore the EDA industry, have moved to using specialized languages and tools that improve the efficiency of the verification process. Previously, verification involved writing a testbench in a hardware description language (HDL) such as Verilog (IEEE-1364) or VHDL (IEEE-1076). By using the same language for design and verification, the processes tend to be a continuum rather than distinct parts. This is a simple mechanism seemingly not requiring additional training, but it has serious shortcomings when applied to very complex problems. Large projects tend to use specialized languages and, in many cases, separate teams of verification engineers working independently from the design team. Two verification languages emerged in the mid-1990s: Verisity's e and System Science's Vera. These two languages have followed two very different paths.