Industrial experience with test generation languages for processor verification
Proceedings of the 41st annual Design Automation Conference
VLIW: a case study of parallelism verification
Proceedings of the 42nd annual Design Automation Conference
IEEE P1647 and P1800: Two approaches to standardization and language design
IEEE Design & Test
Scheduling of transactions for system-level test-case generation
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Supporting sequential assumptions in hybrid verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Distance-guided hybrid verification with GUIDO
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Scheduling-based test-case generation for verification of multimedia SoCs
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Intelligent interleaving of scenarios: a novel approach to system level test generation
Proceedings of the 44th annual Design Automation Conference
on the design of a formal debugger for system architecture
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Using linear programming techniques for scheduling-based random test-case generation
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
RAPANUI: rapid prototyping for media processor architecture exploration
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
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From the Publisher:The Art of Verification with Vera covers the essential elements of VERA with detailed examples demonstrating how the VERA testbench tool and the OpenVera language can be harnessed to effectively verify different types of designs. It helps the reader understand critical verification issues and teaches how to expedite and enhance functional design verification.This book discusses a range of verification issues including test case identification, stimulus generation, results checking, test coverage and test regression. Theses concepts are used to develop a verification strategy and a VERA testbench for a common design. Each component of this testbench is discussed in detail to demonstrate the methodologies presented.Highlights include:Comprehensive discussion of verification strategies for complex System-on-a-chipdesigns.Identifying test cases and testbench components Strategies for stimulusgenerationMonitors and result-checking strategiesHow to Build complex testbenches with VeraUsing Veras classes to do automatic stimulus generators, transactors andmonitorsRun-time constraints with VeraA detailed testbench for the Ethernet MACPractical issues in ASIC VerificationTest space coverage versus code coveragevDebugging strategiesRegressions