Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Validation coverage analysis for complex digital designs
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
Validation with guided search of the state space
DAC '98 Proceedings of the 35th annual Design Automation Conference
Enhancing simulation with BDDs and ATPG
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Probabilistic state space search
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Improving coverage analysis and test generation for large designs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Modeling design constraints and biasing in simulation using BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Automatic lighthouse generation for directed state space search
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A hybrid verification approach: getting deep into the design
Proceedings of the 39th annual Design Automation Conference
Deriving a simulation input generator and a coverage metric from a formal specification
Proceedings of the 39th annual Design Automation Conference
Introduction to Algorithms
Art of Verification with VERA
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Writing Testbenches: Functional Verification of HDL Models, Second Edition
Writing Testbenches: Functional Verification of HDL Models, Second Edition
Using Counter Example Guided Abstraction Refinement to Find Complex Bugs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Defining coverage views to improve functional coverage analysis
Proceedings of the 41st annual Design Automation Conference
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
Hybrid Verification of Protocol Bridges
IEEE Design & Test
An effective guidance strategy for abstraction-guided simulation
Proceedings of the 44th annual Design Automation Conference
Stimulus generation for constrained random simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Auxiliary state machines + context-triggered properties in verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient design validation based on cultural algorithms
Proceedings of the conference on Design, automation and test in Europe
Improved visibility in one-to-many trace concretization
Proceedings of the conference on Design, automation and test in Europe
Constraints in one-to-many concretization for abstraction refinement
Proceedings of the 46th Annual Design Automation Conference
Debugging from high level down to gate level
Proceedings of the 46th Annual Design Automation Conference
Simulation vs. formal: absorb what is useful; reject what is useless
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
An abstraction-guided simulation approach using Markov models for microprocessor verification
Proceedings of the Conference on Design, Automation and Test in Europe
Automatic constraint generation for guided random simulation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Efficient state space exploration: interleaving stateless and state-based model checking
Proceedings of the International Conference on Computer-Aided Design
EverLost: a flexible platform for industrial-strength abstraction-guided simulation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
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Constrained random simulation is a widespread technique used to perform functional verification on complex digital designs, because it can generate simulation vectors at a very high rate. However, the generation of high-coverage tests remains a major challenge even in light of this high performance. In this paper we present Guido, a hybrid verification software that uses formal verification techniques to guide the simulation towards a verification goal. Guido is novel in that 1) it guides the simulation by means of a distance function derived from the circuit structure, and 2) it has a trace sequence controller that monitors and controls the direction of the simulation by striking a balance between random chance and controlled hill-climbing. We present experimental results indicating that Guido can tackle complex designs, including a picoJava microprocessor, and reach a verification goal in far fewer simulation cycles than random simulation.