Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The Stanford FLASH multiprocessor
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
S-connect: from networks of workstations to supercomputer performance
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Computer Networks
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
On Combining Formal and Informal Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Enhancing simulation with BDDs and ATPG
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Symbolic guided search for CTL model checking
Proceedings of the 37th Annual Design Automation Conference
Probabilistic state space search
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Rarity based guided state space search
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Directed explicit model checking with HSF-SPIN
SPIN '01 Proceedings of the 8th international SPIN workshop on Model checking of software
On the Effective Deployment of Functional Formal Verification
Formal Methods in System Design
Model checking Java programs using structural heuristics
ISSTA '02 Proceedings of the 2002 ACM SIGSOFT international symposium on Software testing and analysis
SIVA: A System for Coverage-Directed State Space Search
Journal of Electronic Testing: Theory and Applications
Counterexample-guided choice of projections in approximate symbolic model checking
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Simulation coverage enhancement using test stimulus transformation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Partial Order Reduction in Directed Model Checking
Proceedings of the 9th International SPIN Workshop on Model Checking of Software
Hints to accelerate Symbolic Traversal
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Error Detection with Directed Symbolic Model Checking
FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume I - Volume I
Efficient Decision Procedures for Model Checking of Linear Time Logic Properties
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Property Checking via Structural Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Combining Symmetry Reduction and Under-Approximation for Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
SetA*: an efficient BDD-based heuristic search algorithm
Eighteenth national conference on Artificial intelligence
Property-Specific Testbench Generation for Guided Simulation
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Enhanced Diameter Bounding via Structural
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Heuristic-Based Model Refinement for FLAVERS
Proceedings of the 26th International Conference on Software Engineering
Heuristic-guided counterexample search in FLAVERS
Proceedings of the 12th ACM SIGSOFT twelfth international symposium on Foundations of software engineering
A context-sensitive structural heuristic for guided search model checking
Proceedings of the 20th IEEE/ACM international Conference on Automated software engineering
Efficiently generating test vectors with state pruning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
More efficient on-the-fly LTL verification with Tarjan's algorithm
Theoretical Computer Science - Tools and algorithms for the construction and analysis of systems (TACAS 2004)
Using heuristic search for finding deadlocks in concurrent systems
Information and Computation
Distance-guided hybrid verification with GUIDO
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Guiding simulation with increasingly refined abstract traces
Proceedings of the 43rd annual Design Automation Conference
Fast falsification based on symbolic bounded property checking
Proceedings of the 43rd annual Design Automation Conference
Combining symmetry reduction and under-approximation for symbolic model checking
Formal Methods in System Design
DELFIN+: An efficient deadlock detection tool for CCS processes
Journal of Computer and System Sciences
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
Hybrid Verification of Protocol Bridges
IEEE Design & Test
Formal Verification of Concurrent Systems via Directed Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
An effective guidance strategy for abstraction-guided simulation
Proceedings of the 44th annual Design Automation Conference
A static compliance-checking framework for business process models
IBM Systems Journal
State-set branching: Leveraging BDDs for heuristic search
Artificial Intelligence
Efficient design validation based on cultural algorithms
Proceedings of the conference on Design, automation and test in Europe
Improved visibility in one-to-many trace concretization
Proceedings of the conference on Design, automation and test in Europe
The High Road to Formal Validation
ABZ '08 Proceedings of the 1st international conference on Abstract State Machines, B and Z
Guided model checking for programs with polymorphism
Proceedings of the 2009 ACM SIGPLAN workshop on Partial evaluation and program manipulation
Fundamenta Informaticae - Fundamentals of Software Engineering 2007: Selected Contributions
Survey on Directed Model Checking
Model Checking and Artificial Intelligence
ACM Computing Surveys (CSUR)
Taming numbers and durations in the model checking integrated planning system
Journal of Artificial Intelligence Research
Engineering benchmarks for planning: the domains used in the deterministic part of IPC-4
Journal of Artificial Intelligence Research
GAMBIT: effective unit testing for concurrency libraries
Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
Exploiting Target Enlargement and Dynamic Abstraction within Mixed BDD and SAT Invariant Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Monitoring Interfaces for Faults
Electronic Notes in Theoretical Computer Science (ENTCS)
Language-Emptiness Checking of Alternating Tree Automata Using Symbolic Reachability Analysis
Electronic Notes in Theoretical Computer Science (ENTCS)
Under-approximation Heuristics for Grid-based Bounded Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Using heuristic search for finding deadlocks in concurrent systems
Information and Computation
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
SPIN'03 Proceedings of the 10th international conference on Model checking software
Generating counter-examples through randomized guided search
Proceedings of the 14th international SPIN conference on Model checking software
Simulation vs. formal: absorb what is useful; reject what is useless
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
Using virtual coverage to hit hard-to-reach events
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
An abstraction-guided simulation approach using Markov models for microprocessor verification
Proceedings of the Conference on Design, Automation and Test in Europe
Biased model checking using flows
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
SAT-based semiformal verification of hardware
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Statically-directed dynamic automated test generation
Proceedings of the 2011 International Symposium on Software Testing and Analysis
Finding bugs in network protocols using simulation code and protocol-specific heuristics
ICFEM'05 Proceedings of the 7th international conference on Formal Methods and Software Engineering
Efficient state space exploration: interleaving stateless and state-based model checking
Proceedings of the International Conference on Computer-Aided Design
EverLost: a flexible platform for industrial-strength abstraction-guided simulation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Parallel external directed model checking with linear i/o
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
Abstraction-Guided model checking using symbolic IDA* and heuristic synthesis
FORTE'05 Proceedings of the 25th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
Directed model checking with distance-preserving abstractions
SPIN'06 Proceedings of the 13th international conference on Model Checking Software
Adapting an AI planning heuristic for directed model checking
SPIN'06 Proceedings of the 13th international conference on Model Checking Software
Fundamenta Informaticae - Fundamentals of Software Engineering 2007: Selected Contributions
Guided Model Checking with a Bayesian Meta-heuristic
Fundamenta Informaticae - APPLICATION OF CONCURRENCY TO SYSTEM DESIGN (ACSD'04)
System level formal verification via model checking driven simulation
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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In practice, model checkers are most useful when they find bugs, not when they prove a property. However, because large portions of the state space of the design actually satisfy the specification, model checkers devote much effort verifying correct portions of the design. In this paper, we enhance the bug-finding capability of a model checker by using heuristics to search the states that are most likely to lead to an error, first. Reductions of 1 to 3 orders of magnitude in the number of states needed to find bugs in industrial designs have been observed. Consequently, these heuristics can extend the capability of model checkers to find bugs in designs.