A VLSI architecture for concurrent data structures
A VLSI architecture for concurrent data structures
Computer
The design and analysis of DASH: a scalable directory-based multiprocessor
The design and analysis of DASH: a scalable directory-based multiprocessor
Compressionless routing: a framework for adaptive and fault-tolerant routing
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
A communication architecture for multiprocessor networks
A communication architecture for multiprocessor networks
Missing the memory wall: the case for processor/memory integration
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
IEEE Transactions on Parallel and Distributed Systems
Validation with guided search of the state space
DAC '98 Proceedings of the 35th annual Design Automation Conference
A Testbed for Evaluation of Fault-Tolerant Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
Piranha: a scalable architecture based on single-chip multiprocessing
Proceedings of the 27th annual international symposium on Computer architecture
Exploiting Network Locality for CC-NUMA Multiprocessors
The Journal of Supercomputing
An Application-Driven Study of Multicast Communication for Write Invalidation
The Journal of Supercomputing
MediaWorm: A QoS Capable Router Architecture for Clusters
IEEE Transactions on Parallel and Distributed Systems
The Thread-Based Protocol Engines for CC-NUMA Multiprocessors
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
Merging, sorting and matrix operations on the SOME-bus multiprocessor architecture
Future Generation Computer Systems - Special issue: Advanced services for clusters and internet computing
The ParaStation project: Using workstations as building blocks for parallel computing
Information Sciences: an International Journal
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S-Connect is a new high speed, scalable interconnect system that has been developed to support networks of workstations to efficiently share computing resources. It uses off-the-shelf CMOS technology to directly drive fiber-optic systems at speeds greater than 1 Gbit/sec and can realize bisection bandwidths comparable to high-end MPP systems while being >10x more cost-effective. S-Connect systems do not rely on centralized switches, but rather are composed of adaptive, topology independent routing elements that are integrated into each node. The S-Connect routing algorithm is optimized for fine grained, irregular traffic and is designed to support high traffic loads, that can utilize most of the physically available bandwidth. Such traffic is typical of a distributed shared memory system, which is one of the intended applications. S-Connect innovations include a novel distributed phase locking method that allows global synchronization, HW support for multiple message priorities, in-band monitoring and control facilities, and a low overhead channel protocol that supports multiple in-transit messages on the same fiber.The first version of the S-Connect switching element has been successfully implemented in a commercial, 0.65 µm CMOS process.