Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Model checking, abstraction, and compositional verification
Model checking, abstraction, and compositional verification
Tearing based automatic abstraction for CTL model checking
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Validation with guided search of the state space
DAC '98 Proceedings of the 35th annual Design Automation Conference
C-based synthesis experiences with a behavior synthesizer, “cyber”
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
Proceedings of the 37th Annual Design Automation Conference
Probabilistic state space search
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
On Combining Formal and Informal Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Systematic functional coverage metric synthesis from hierarchical temporal event relation graph
Proceedings of the 41st annual Design Automation Conference
Test generation games from formal specifications
Proceedings of the 43rd annual Design Automation Conference
An effective guidance strategy for abstraction-guided simulation
Proceedings of the 44th annual Design Automation Conference
Improved visibility in one-to-many trace concretization
Proceedings of the conference on Design, automation and test in Europe
Simulation vs. formal: absorb what is useful; reject what is useless
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
Automatic constraint generation for guided random simulation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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Simulation continues to be the primary technique for functional validation of designs. It is important that simulation vectors be effective in targeting the types of bugs designers expect to find rather than some generic coverage metrics. The overall focus of our work is to generate a property-specific testbench for guided simulation, that is targeted either at proving the correctness of a property or at finding a bug. This is facilitated by generation of a property-specific model, called a "Witness Graph", which captures interesting paths in the design. Starting from an initial abstract model of the design, symbolic model checking, pruning, and refinement steps are applied in an iterative manner, until either a conclusive result is obtained or computing resources are exhausted. This paper describes the theoretical underpinnings of generating and using a Witness Graph for CTL correctness properties, practical issues related to the generation of a testbench, and experiences with an industrial example. We have been able to demonstrate on a real in-house design that such an approach can lead to significant reduction in the time required to analyze the design for a CTL property and find a witness.