On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Using model checking to generate tests from requirements specifications
ESEC/FSE-7 Proceedings of the 7th European software engineering conference held jointly with the 7th ACM SIGSOFT international symposium on Foundations of software engineering
Deriving a simulation input generator and a coverage metric from a formal specification
Proceedings of the 39th annual Design Automation Conference
Executable Protocol Specification in ESL
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Using a formal specification and a model checker to monitor and direct simulation
Proceedings of the 40th annual Design Automation Conference
Property-Specific Testbench Generation for Guided Simulation
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Verifying Properties Using Sequential ATPG
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Using Model Checking to Generate Tests from Specifications
ICFEM '98 Proceedings of the Second IEEE International Conference on Formal Engineering Methods
SAT based solutions for consistency problems in formal property specifications for open systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Integrated verification approach during ADL-driven processor design
Microelectronics Journal
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In this paper, we present methods for automatic test generation from formal specifications.These are used to create intelligent test benches that are able to cover corner case behaviors in much less time.We have developed a prototype tool for intelligent test generation within the layered test bench architecture proposed in RVM.We present results on verification IPs of standard bus protocols to show the effectiveness of our approach.