Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Introduction to algorithms
Model checking
Modeling design constraints and biasing in simulation using BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Introduction to the Theory of Computation: Preliminary Edition
Introduction to the Theory of Computation: Preliminary Edition
Simple on-the-fly automatic verification of linear temporal logic
Proceedings of the Fifteenth IFIP WG6.1 International Symposium on Protocol Specification, Testing and Verification XV
Monitor-Based Formal Specification of PCI
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
A Theory of Consistency for Modular Synchronous Systems
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
Alternating-time Temporal Logic
FOCS '97 Proceedings of the 38th Annual Symposium on Foundations of Computer Science
Deriving a simulation input generator and a coverage metric from a formal specification
Proceedings of the 39th annual Design Automation Conference
Monitor-Based Formal Specification of PCI
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A Theory of Consistency for Modular Synchronous Systems
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
XFM: An incremental methodology for developing formal models
ACM Transactions on Design Automation of Electronic Systems (TODAES)
XFM: extreme formal method for capturing formal specification into abstract models
Formal methods and models for system design
Test generation games from formal specifications
Proceedings of the 43rd annual Design Automation Conference
BUSpec: A framework for generation of verification aids for standard bus protocol specifications
Integration, the VLSI Journal
Simulation bounds for equivalence verification of polynomial datapaths using finite ring algebra
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coalgebraic logic and synthesis of mealy machines
FOSSACS'08/ETAPS'08 Proceedings of the Theory and practice of software, 11th international conference on Foundations of software science and computational structures
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Hardware specifications in English are frequently ambiguous and often self-contradictory.We propose a new logic ESL which facilitates formal specification of hardware protocols. Our logic is closely related to LTL but can express all regular safety properties. We have developed a protocol synthesis methodology which generates Mealy machines from ESL specifications. The Mealy machines can be automatically translated into executable code either in Verilog or SMV. Our methodology exploits the observation that protocols are naturally composed of many semantically distinct components. This structure is reflected in the syntax of ESL specifications. We use a modified LTL tableau construction to build a Mealy machine for each component. The Mealy machines are connected together in a Verilog or SMV framework. In many cases this makes it possible to circumvent the state explosion problem during code generation and to identify conflicts between components during simulation or model checking. We have implemented a tool based on the logic and used it to specify and verify a significant part of the PCI bus protocol.