Statecharts: A visual formalism for complex systems
Science of Computer Programming
Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
PCI system architecture (4th ed.)
PCI system architecture (4th ed.)
Formal verification of an IBM CoreConnect processor local bus arbiter core
Proceedings of the 37th Annual Design Automation Conference
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Verifying the performance of the PCI local bus using symbolic techniques
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
What is in a Step: On the Semantics of Statecharts
TACS '91 Proceedings of the International Conference on Theoretical Aspects of Computer Software
Executable Protocol Specification in ESL
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Monitor-Based Formal Specification of PCI
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
The ForSpec Temporal Logic: A New Temporal Property-Specification Language
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Coverage of Implementations by Simulating Specifications
TCS '02 Proceedings of the IFIP 17th World Computer Congress - TC1 Stream / 2nd IFIP International Conference on Theoretical Computer Science: Foundations of Information Technology in the Era of Networking and Mobile Computing
Quality and Single-Stuck Faults
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Using Live Sequence Charts for Hardware Protocol Specification and Compliance Verification
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
On the Use of a High-Level Fault Model to Check Properties Incompleteness
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 1
ELF-Murphy Data on Defects and Test Sets
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Proposal for Transaction-Level Verification with Component Wrapper Language
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Parameterized Specification and Verification of the Chilean Electronic Invoices System
QEST '04 Proceedings of the The Quantitative Evaluation of Systems, First International Conference
On Parameter Synthesis by Parallel Model Checking
IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB)
| Hi-index | 0.00 |
A typical verification intellectual property (VIP) of a bus protocol such as ARM advanced micro-controller bus architecture (AMBA) or PCI consists of a set of assertions and associated verification aids such as test-benches, design-ware models and coverage metrics. While several languages have been formalized for specifying assertions (examples include Open-Vera Assertions, Sugar, ForSpec, System Verilog Assertions, etc.), it is widely accepted that the tasks of writing protocol-compliant models and test-benches that produce protocol compliant stimuli are also tasks of equal importance. In this paper, we present a platform for high-level specification of a bus protocol in a hierarchical manner and an automated methodology for generating a variety of verification aids that supplement the set of assertions in a VIP. We also show that the verification aids can be efficiently used to determine the completeness of the set of assertions in a simulation-based verification environment.