Deriving a simulation input generator and a coverage metric from a formal specification
Proceedings of the 39th annual Design Automation Conference
Hole analysis for functional coverage data
Proceedings of the 39th annual Design Automation Conference
Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers
Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
System-on-chip validation using UML and CWL
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
VYRD: verifYing concurrent programs by runtime refinement-violation detection
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Guiding simulation with increasingly refined abstract traces
Proceedings of the 43rd annual Design Automation Conference
Test generation games from formal specifications
Proceedings of the 43rd annual Design Automation Conference
Runtime Refinement Checking of Concurrent Data Structures
Electronic Notes in Theoretical Computer Science (ENTCS)
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We describe a technique for verifying that a hardware design correctly implements a protocol-level formal specification. Simulation steps are translated to protocol state transitions using a refinement map and then verified against the specification using a model checker. On the specification state space, the model checker collects coverage information and identifies states violating certain properties. It then generates protocol-level traces to these coverage gaps and error states. This technique was applied to the multiprocessing hardware of the Alpha 21364 microprocessor and the cache coherence protocol. We were able to generate an error trace which exercised a bug in the implementation that had not been discovered before a prototype was built.