On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Alternating-time temporal logic
Journal of the ACM (JACM)
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
QUBE: A System for Deciding Quantified Boolean Formulas Satisfiability
IJCAR '01 Proceedings of the First International Joint Conference on Automated Reasoning
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Test generation games from formal specifications
Proceedings of the 43rd annual Design Automation Conference
Checking sanity of software requirements
SEFM'12 Proceedings of the 10th international conference on Software Engineering and Formal Methods
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Formal property verification is increasingly being adopted by designers for module level validation. The behavior of a module is typically expressed in terms of the behavioral guarantee of the module under assumptions on its environment. Expressing such assume-guarantee properties correctly in a formal language is a nontrivial task and errors in the specification are not uncommon. In this paper we examine the main forms of specification errors for open systems, and present SAT based algorithms for verifying the specification against such errors.