Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
GRASP—a new search algorithm for satisfiability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Symbolic Model Checking
SAT-Based Image Computation with Application in Reachability Analysis
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Symbolic Reachability Analysis Based on SAT-Solvers
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
SAT and ATPG: Boolean engines for formal hardware verification
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
SAT-based unbounded symbolic model checking
Proceedings of the 40th annual Design Automation Conference
A Novel SAT All-Solutions Solver for Efficient Preimage Computation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Safety Property Verification Using Sequential SAT and Bounded Model Checking
IEEE Design & Test
Abstraction refinement by controllability and cooperativeness analysis
Proceedings of the 41st annual Design Automation Conference
SATORI - A Fast Sequential SAT Engine for Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Design diagnosis using Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Efficient reachability checking using sequential SAT
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Predicate Abstraction of ANSI-C Programs Using SAT
Formal Methods in System Design
Efficient Preimage Computation Using A Novel Success-Driven ATPG
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Success-Driven Learning in ATPG for Preimage Computation
IEEE Design & Test
SAT-Based Complete Don't-Care Computation for Network Optimization
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Faster Counterexample Minimization Algorithm Based on Refutation Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An Efficient Sequential SAT Solver With Improved Search Strategies
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Forward image computation with backtracing ATPG and incremental state-set construction
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Beyond safety: customized SAT-based model checking
Proceedings of the 42nd annual Design Automation Conference
Prime clauses for fast enumeration of satisfying assignments to boolean circuits
Proceedings of the 42nd annual Design Automation Conference
Fully Symbolic Unbounded Model Checking for Alternating-time Temporal Logic1
Autonomous Agents and Multi-Agent Systems
Model Checking C Programs Using F-SOFT
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
State Set Management for SAT-based Unbounded Model Checking
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Checking consistency of C and Verilog using predicate abstraction and induction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ATPG-based preimage computation: efficient search space pruning with ZBDD
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
SAT based solutions for consistency problems in formal property specifications for open systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Transition-by-transition FSM traversal for reachability analysis in bounded model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Verification of large scale nano systems with unreliable nano devices
Nano, quantum and molecular computing
Automatic invariant strengthening to prove properties in bounded model checking
Proceedings of the 43rd annual Design Automation Conference
From Bounded to Unbounded Model Checking for Temporal Epistemic Logic
Fundamenta Informaticae - Multiagent Systems (FAMAS'03)
Expressing and Verifying Temporal and Structural Properties of Mobile Agents
Fundamenta Informaticae - SPECIAL ISSUE ON CONCURRENCY SPECIFICATION AND PROGRAMMING (CS&P 2005) Ruciane-Nide, Poland, 28-30 September 2005
Stepping forward with interpolants in unbounded model checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Verification method of dataflow algorithms in high-level synthesis
Journal of Systems and Software
Interpolant Learning and Reuse in SAT-Based Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Boosting the role of inductive invariants in model checking
Proceedings of the conference on Design, automation and test in Europe
Alembic: an efficient algorithm for CNF preprocessing
Proceedings of the 44th annual Design Automation Conference
Symbolic model checking of institutions
Proceedings of the ninth international conference on Electronic commerce
Boosting interpolation with dynamic localized abstraction and redundancy removal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Symbolic model checking for temporal-epistemic logics
ACM SIGACT News
Proceedings of the 6th international joint conference on Autonomous agents and multiagent systems
Bounded Model Checking for the Existential Fragment of TCTL_{-G} and Diagonal Timed Automata
Fundamenta Informaticae
Automatic symbolic compositional verification by learning assumptions
Formal Methods in System Design
Model checking with Boolean Satisfiability
Journal of Algorithms
Efficient SAT-based bounded model checking for software verification
Theoretical Computer Science
A View from the Engine Room: Computational Support for Symbolic Model Checking
25 Years of Model Checking
Literal Projection for First-Order Logic
JELIA '08 Proceedings of the 11th European conference on Logics in Artificial Intelligence
Automated abstraction by incremental refinement in interpolant-based model checking
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
VerICS 2007 - a Model Checker for Knowledge and Real-Time
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
SAT-based Unbounded Model Checking of Timed Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
Trading-off SAT search and variable quantifications for effective unbounded model checking
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
The synergy of precise and fast abstractions for program verification
Proceedings of the 2009 ACM symposium on Applied Computing
Contradictory antecedent debugging in bounded model checking
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Boolean satisfiability from theoretical hardness to practical success
Communications of the ACM - A Blind Person's Interaction with Technology
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
Hybrid BDD and All-SAT Method for Model Checking
Languages: From Formal to Natural
Quantifier Elimination via Functional Composition
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Model checking: algorithmic verification and debugging
Communications of the ACM - Scratch Programming for All
On compiling system models for faster and more scalable diagnosis
AAAI'05 Proceedings of the 20th national conference on Artificial intelligence - Volume 1
Journal of Artificial Intelligence Research
Synthesizing complementary circuits automatically
Proceedings of the 2009 International Conference on Computer-Aided Design
Tableaux for Projection Computation and Knowledge Compilation
TABLEAUX '09 Proceedings of the 18th International Conference on Automated Reasoning with Analytic Tableaux and Related Methods
Computing Over-Approximations with Bounded Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Automatic fault localization for property checking
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
An interpolation method for CLP traversal
CP'09 Proceedings of the 15th international conference on Principles and practice of constraint programming
Improvements to hybrid incremental SAT algorithms
SAT'08 Proceedings of the 11th international conference on Theory and applications of satisfiability testing
Partitioning interpolant-based verification for effective unbounded model checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Solving satisfiability problems with preferences
Constraints
Synthesizing complementary circuits automatically
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Making deduction more effective in SAT solvers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
New algorithm for weak monadic second-order logic on inductive structures
CSL'10/EACSL'10 Proceedings of the 24th international conference/19th annual conference on Computer science logic
A novel SAT-based approach to the task graph cost-optimal scheduling problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SAT-based model checking without unrolling
VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
Bisimulation conversion and verification procedure for goal-based control systems
Formal Methods in System Design
Sechecker: a sequential equivalence checking framework based on K th invariants
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Approximate quantifier elimination for propositional boolean formulae
NFM'11 Proceedings of the Third international conference on NASA Formal methods
Model checking using SMT and theory of lists
NFM'11 Proceedings of the Third international conference on NASA Formal methods
SAT-based semiformal verification of hardware
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Computing small unsatisfiable cores in satisfiability modulo theories
Journal of Artificial Intelligence Research
Existential quantification as incremental SAT
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Linear completeness thresholds for bounded model checking
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Abstraction and refinement in model checking
FMCO'05 Proceedings of the 4th international conference on Formal Methods for Components and Objects
Predicate abstraction of RTL verilog descriptions using constraint logic programming
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Minimizing counterexample with unit core extraction and incremental SAT
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
Verifying multi-agent systems via unbounded model checking
FAABS'04 Proceedings of the Third international conference on Formal Approaches to Agent-Based Systems
Applications of craig interpolants in model checking
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Efficient conflict analysis for finding all satisfying assignments of a boolean circuit
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
DiVer: SAT-based model checking platform for verifying large scale systems
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Applying constraint logic programming to predicate abstraction of RTL verilog descriptions
MICAI'05 Proceedings of the 4th Mexican international conference on Advances in Artificial Intelligence
Predicate abstraction via symbolic decision procedures
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Symmetry reduction in SAT-based model checking
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Symbolic compositional verification by learning assumptions
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Achieving speedups in distributed symbolic reachability analysis through asynchronous computation
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
An analysis of SAT-based model checking techniques in an industrial environment
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
IC3: where monolithic and incremental meet
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Counting models in integer domains
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Building efficient decision procedures on top of SAT solvers
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Efficient abstraction refinement in interpolation-based unbounded model checking
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Formal Methods in System Design
SBMC: symmetric bounded model checking
VECoS'10 Proceedings of the Fourth international conference on Verification and Evaluation of Computer and Communication Systems
Inferring definite counterexamples through under-approximation
NFM'12 Proceedings of the 4th international conference on NASA Formal Methods
Symbolic model checking for temporal-epistemic logic
Logic Programs, Norms and Action
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
On the Magnitude of Completeness Thresholds in Bounded Model Checking
LICS '12 Proceedings of the 2012 27th Annual IEEE/ACM Symposium on Logic in Computer Science
Incremental, inductive CTL model checking
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
DNF hypotheses in explanatory induction
ILP'11 Proceedings of the 21st international conference on Inductive Logic Programming
Abstraction for model checking modular interpreted systems over ATL
ProMAS'11 Proceedings of the 9th international conference on Programming Multi-Agent Systems
SAT-based Unbounded Model Checking of Timed Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
VerICS 2007 - a Model Checker for Knowledge and Real-Time
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
Bounded Model Checking for the Existential Fragment of TCTL$_{-G}$ and Diagonal Timed Automata
Fundamenta Informaticae
Expressing and Verifying Temporal and Structural Properties of Mobile Agents
Fundamenta Informaticae - SPECIAL ISSUE ON CONCURRENCY SPECIFICATION AND PROGRAMMING (CS&P 2005) Ruciane-Nide, Poland, 28-30 September 2005
From Bounded to Unbounded Model Checking for Temporal Epistemic Logic
Fundamenta Informaticae - Multiagent Systems (FAMAS'03)
Theories, solvers and static analysis by abstract interpretation
Journal of the ACM (JACM)
ALLQBF solving by computational learning
ATVA'12 Proceedings of the 10th international conference on Automated Technology for Verification and Analysis
Computing interpolants without proofs
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
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A method of symbolic model checking is introduced that uses conjunctive normal form (CNF) rather than binary decision diagrams (BDD's) and uses a SAT-based approach to quantifier elimination. This method is compared to a traditional BDD-based model checking approach using a set of benchmark problems derived from the compositional verification of a commercial microprocessor design.