A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
Model checking
Chaff: engineering an efficient SAT solver
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SAT-Based Image Computation with Application in Reachability Analysis
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
A Novel SAT All-Solutions Solver for Efficient Preimage Computation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Safety Property Verification Using Sequential SAT and Bounded Model Checking
IEEE Design & Test
Efficient reachability checking using sequential SAT
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Faster Counterexample Minimization Algorithm Based on Refutation Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An Efficient Sequential SAT Solver With Improved Search Strategies
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Forward image computation with backtracing ATPG and incremental state-set construction
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
State Set Management for SAT-based Unbounded Model Checking
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ATPG-based preimage computation: efficient search space pruning with ZBDD
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
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Nano, quantum and molecular computing
Verification method of dataflow algorithms in high-level synthesis
Journal of Systems and Software
Interpolant Learning and Reuse in SAT-Based Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Boosting interpolation with dynamic localized abstraction and redundancy removal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Model checking with Boolean Satisfiability
Journal of Algorithms
Automated abstraction by incremental refinement in interpolant-based model checking
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Trading-off SAT search and variable quantifications for effective unbounded model checking
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
A novel formal verification approach for RTL hardware IP cores
Computer Standards & Interfaces
Partitioning interpolant-based verification for effective unbounded model checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sechecker: a sequential equivalence checking framework based on K th invariants
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Model checking using SMT and theory of lists
NFM'11 Proceedings of the Third international conference on NASA Formal methods
On subsumption removal and on-the-fly CNF simplification
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
Minimizing counterexample with unit core extraction and incremental SAT
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
Efficient conflict analysis for finding all satisfying assignments of a boolean circuit
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Symmetry reduction in SAT-based model checking
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Achieving speedups in distributed symbolic reachability analysis through asynchronous computation
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
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This paper describes a SAT-based unbounded symbolic model checking algorithm. BDDs have been widely used for symbolic model checking, but the approach suffers from memory overflow. The SAT procedure was exploited to overcome the problem, but it verified only the states reachable through a bounded number of transitions. The proposed algorithm deals with unbounded symbolic model checking. The conjunctive normal form is used to represent sets of states and the transition relation, and a SAT procedure is modified to compute the existential quantification required in obtaining a pre-image. Some optimization techniques are exploited, and the depth first search method is used for efficient safety-property checking. Experimental results show the proposed algorithm can check more circuits than BDD-based symbolic model checking tools.