The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Model checking
A machine program for theorem-proving
Communications of the ACM
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Property Checking via Structural Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
SAT-based unbounded symbolic model checking
Proceedings of the 40th annual Design Automation Conference
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
SATORI - A Fast Sequential SAT Engine for Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient reachability checking using sequential SAT
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Functional test generation using property decompositions for validation of pipelined processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Verification method of dataflow algorithms in high-level synthesis
Journal of Systems and Software
Specification-driven directed test generation for validation of pipelined processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Functional test generation using design and property decomposition techniques
ACM Transactions on Embedded Computing Systems (TECS)
Hybrid BDD and All-SAT Method for Model Checking
Languages: From Formal to Natural
Automated data analysis solutions to silicon debug
Proceedings of the Conference on Design, Automation and Test in Europe
Automating data analysis and acquisition setup in a silicon debug environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The common view of model checking is as a supplementary methodology to improve the quality of simulation-based functional verification. Traditional model checking relies on BDD- or combinational-SAT-based approaches for search. The authors discuss the potential to apply a sequential SAT solver in model checking, comparing its performance against BDD- and combinational-SAT-based approaches.